1. Field of the Invention
The present invention relates to electronic packages and semiconductor devices using the same and, particularly, to a package for an electronic component made of a rectangular metal plate and a semiconductor device using the same.
2. Description of Related Art
Electronic circuits having a semiconductor device are required to reduce the size of each electronic package in order to meet the recent demand for higher integration. Chip Scale Package (CSP) technology has been proposed to reduce the package size of semiconductor devices.
Japanese Unexamined Patent Publication No. 2004-40008 describes an example of the CSP semiconductor device. FIG. 8 is the perspective view of this semiconductor device and FIG. 9 is a perspective view of the structure when mounting the semiconductor device to a substrate. As shown in FIGS. 8 and 9, the semiconductor device has a semiconductor chip 109 which is mounted to an inner base part 102 of a metal base 103. The semiconductor chip 109 has a gate electrode 111a and a source electrode 111b on its surface. The metal base 103 has U-shaped both side parts 105 which are opposed to each other. A plurality of drain connection electrodes 104 are formed in the ends of the U-shaped parts. The chip mounting part (base part) 102 of the metal base 103 is designed to be slightly larger than the semiconductor chip 109.
As shown in FIG. 9, the semiconductor device is soldered to a substrate 130 in a face-down configuration. If the soldering areas of the surface electrodes 111a and 111b and the soldering areas of the connection electrodes 104 are significantly different from each other or they are arranged off-balance, for example, a great difference occurs in the force generated by soldering surface tension, soldering stress, and soldering thermal expansion. This causes displacement in mounting position or breakdown.
When solder is heated to reflow, it is melted and thereby surface tension occurs. The surface tension increases in proportion to the size of the mounting area to be soldered and acts toward the center of the mounting area. Therefore, a difference in surface tension occurs due to a difference in area size or arrangement balance. Further, when the solder is cooled after heating, it hardens and stress which is similar to the surface tension which has occurred during heating is left in the solder, and thereby breakdown is likely to occur due to a difference in stress. Furthermore, when the semiconductor device is heated after mounting by operation or environment, the substrate, metal base, semiconductor chip are thermally expanded and the solder is stressed due to a difference in the coefficient of thermal expansion and thus subject to breakdown.
To avoid the above drawbacks, this conventional semiconductor device makes the soldering areas of the surface electrodes 111a and 111b and those of the connection electrodes 104 which are soldered to the substrate 130 substantially the same size, and disperses the surface electrodes 111a and 111b and the connection electrodes 104 properly. The fixation strength of the surface electrodes 111a and 111b to the substrate 130 and that of the connection electrodes 104 to the substrate 130 thereby substantially equal and balance out. No excess stress is thus left on the mounting areas of the surface electrodes 111a and 111b, thereby preventing the semiconductor device from breaking down due to stress.
FIG. 10 shows the structure of another conventional semiconductor device. This semiconductor device has a rectangular metal package base 103a which has a hollow where a semiconductor chip is to be mounted. An integrated connection electrode 104a is formed in the four sides 105a of the rectangular base. The metal package base 103a has a chip mounting area 102a where a semiconductor chip 109a having a maximum mount size which is slightly smaller than the chip mounting area 102a is mounted by soldering. The semiconductor chip 109a has a plurality of surface electrodes 111 on its surface, and a plurality of soldering bumps 112 on the surface electrodes 111. In this structure, the four sides of the semiconductor chip 109a are pulled in four directions by solder surface tension which occurs with four inner walls 114 of the hollow of the chip mounting area 102a in the metal package base 103a and balance out, thereby providing stable positional accuracy.
In this way, when mounting the semiconductor chip with a maximum mount size to the semiconductor device of FIG. 10, the mounting position can be fixed by self-alignment. However, when mounting a semiconductor chip which is smaller than the maximum mount size to the center part of the chip mounting area 102a, it is difficult to obtain the mechanical positional accuracy of ±50 μm or below. It is also difficult to accurately fix the semiconductor chip to a given center position of the chip mounting area 102a since the chip moves in the flowing direction of solder. For example, if one direction of the semiconductor chip is the width direction and when mounting the semiconductor chip whose size in the width direction is the same as that of the semiconductor chip of the maximum mount size and whose size in the length direction perpendicular to the width direction is about half of the maximum mount size, mounting the semiconductor chip in the center part of the chip mounting area 102a results in that the semiconductor chip moves in the length direction due to the flowing solder which has been melted by heating, thus failing to obtain high positional accuracy.
On the other hand, when mounting the semiconductor chip against the end of the side of the chip mounting area 102a which is parallel to the width direction, the three sides of the semiconductor chip are pulled by the surface tension which occurs with the three inner walls 114 of the chip mounting area 102a and balance out. It is thereby possible to obtain high mounting position accuracy of the semiconductor chip as is the case when mounting the semiconductor chip of the maximum mount size.
In this way, the conventional semiconductor device is capable of obtaining high mounting position accuracy even if the semiconductor chip is shorter in the length direction by mounting the three sides of the semiconductor chips in near proximity to the three inner walls of the chip mounting area in the metal package base. However, the following problems still remain. If the semiconductor device where the semiconductor chip with half the length is face-down mounted to a substrate, a total of the soldering areas of the four connection electrodes which are soldered to the substrate is significantly larger than a total of the soldering areas of the plurality of surface electrodes. This makes a great difference in fixation strength to the substrate between the surface electrodes and the connection electrodes. Further, the soldering areas of the plurality of surface electrodes are arranged asymmetrically, disproportionately to one side, with respect to the soldering areas of the four connection electrodes, compared to the case of mounting the semiconductor chip of the maximum mount size.
This makes a great difference in the force generated by soldering surface tension, soldering stress and soldering thermal expansion between the mounting areas of the connection electrodes and those of the surface electrodes, causing displacement in mounting position or breakdown.